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never stop thinking. microcontrollers data sheet, dec. 2000 c505 c505c c505a c505ca 8-bit single-chip microcontroller
edition 2000-12 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2000. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, dec. 2000 never stop thinking. c505 c505c c505a c505ca 8-bit single-chip microcontroller
controller area network (can): license of robert bosch gmbh c505/c505c/c505a/c505ca data sheet revision history : current version : 2000-12 previous releases : 08.00, 06.00, 07.99, 12.97 page (in previous version page (in current version) subjects (major changes since last revision) 24 24 version register vr2 for c505a-4r/c505ca-4r bb step is updated. we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 12.00 c505/c505c/c505a/ c505ca 8-bit single-chip microcontroller c500 family advance information fully compatible to standard 8051 microcontroller superset of the 8051 architecture with 8 datapointers up to 20 mhz operating frequency ? 375 ns instruction cycle time @16 mhz ? 300 ns instruction cycle time @20 mhz (50 % duty cycle) on-chip program memory (with optional memory protection) ? c505(c)(a)-2r : 16k byte on-chip rom ? c505a-4r/c505ca-4r: 32k byte on-chip rom ? c505a-4e/c505ca-4e: 32k byte on-chip otp ? alternatively up to 64k byte external program memory 256 byte on-chip ram on-chip xram ? c505/c505c : 256 byte ? c505a/c505ca : 1k byte (more features on next page) figure 1 c505 functional units oscillator watchdog timer c500 8-bit usart i/o i/o 8 digit. i/o i/o ram xram on-chip emulation support module timer 2 watchdog timer 8 analog inputs / full-can controller 8 datapointers i/o (2-bit i/o port) port 0 port 1 port 2 port 4 port 3 c505/c505c : 8-bit a/d converter c505a/c505ca : 10-bit c505c/c505ca only c505(c)(a)-2r : 16k rom c505a-4r/c505ca-4r : 32k rom c505a-4e/c505ca-4e : 32k otp c505/c505c: 256 byte c505a/c505ca: 1k byte 256 byte program memory 0 timer 1 core
c505/c505c/c505a/c505ca data sheet 2 12.00 features (continued) : 32 + 2 digital i/o lines ? four 8-bit digital i/o ports ? one 2-bit digital i/o port (port 4) ? port 1 with mixed analog/digital i/o capability three 16-bit timers/counters ? timer 0 / 1 (c501 compatible) ? timer 2 with 4 channels for 16-bit capture/compare operation full duplex serial interface with programmable baudrate generator (usart) full can module, version 2.0 b compliant (c505c and c505ca only) ? 256 register/data bytes located in external data memory area ? 1 mbaud can baudrate when operating frequency is equal to or above 8 mhz ? internal can clock prescaler when input frequency is over 10 mhz on-chip a/d converter ? up to 8 analog inputs ? c505/c505c : 8-bit resolution ? c505a/c505ca: 10-bit resolution twelve interrupt sources with four priority levels on-chip emulation support logic (enhanced hooks technology tm ) programmable 15-bit watchdog timer oscillator watchdog fast power on reset power saving modes ? slow-down mode ? idle mode (can be combined with slow-down mode) ? software power-down mode with wake up capability through p3.2/int0 or p4.1/rxdc pin p-mqfp-44 package pin configuration is compatible to c501, c504, c511/c513-family temperature ranges: sab-c505 versions t a = 0 to 70 c saf-c505 versions t a = -40 to 85 c sah-c505 versions t a = -40 to 110 c sak-c505 versions t a = -40 to 125 c
c505/c505c/c505a/c505ca data sheet 3 12.00 note: the term c505 refers to all versions described within this document unless otherwise noted. however the term c505 may also be restricted by the context to refer to only can-less derivatives with 8-bit adc which are c505-2r and c505-l in this document. note: the term c505(c)(a)-2r, for simplicity, is used to stand for c505 16k byte rom versions within this document which are c505-2r, c505c-2r, c505a-2r and c505ca-2r. ordering information the ordering code for infineon technologies? microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set the specificed temperature rage the package and the type of delivery for the available ordering codes for the c505 please refer to the ? product information microcontrollers ?, which summarizes all available microcontroller variants. table 1 differences in functionality of the c505 mcus device internal program memory xram size a/d converter resolution can controller rom otp c505-2r 16k byte ? 256 byte 8 bit ? c505-l ? ? 256 byte 8 bit ? c505c-2r 16k byte ? 256 byte 8 bit c505c-l ? ? 256 byte 8 bit c505a-4r 32k byte ? 1k byte 10 bit ? c505a-2r 16k byte ? 1k byte 10 bit ? c505a-l ? ? 1k byte 10 bit ? c505ca-4r 32k byte ? 1k byte 10 bit c505ca-2r 16k byte ? 1k byte 10 bit c505ca-l ? ? 1k byte 10 bit c505a-4e ? 32k byte 1k byte 10 bit ? c505ca-4e ? 32k byte 1k byte 10 bit
c505/c505c/c505a/c505ca data sheet 4 12.00 figure 2 logic symbol note: the ordering codes for the mask-rom versions are defined for each product after verification of the respective rom code. port 0 8-bit digital i/o port 1 8-bit digital i/o / port 2 8-bit digital i/o port 3 8-bit digital i/o xtal1 xtal2 reset ea ale psen v aref v dd v ss v agnd 8-bit analog inputs port 4 2-bit digital i/o c505 c505c c505a c505ca
c505/c505c/c505a/c505ca data sheet 5 12.00 figure 3 c505 pin configuration p-mqfp-44 package (top view) this pin functionality is not available in the c505/c505a. p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea p4.1 / rxdc p2.5 / a13 ale p2.6 / a14 p2.7 / a15 psen p2.4 / a12 p2.3 / a11 p2.2 / a10 p2.1 / a9 p2.0 / a8 v dd xtal1 xtal2 p3.7 / rd p3.6 / wr v ss 33 34 35 36 37 38 39 40 41 42 43 44 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1234567 89 10 11 p1.5 / an5 / t2ex p1.6 / an6 / clkout p1.7 / an7 / t2 reset p3.0 / rxd p3.1 / txd p3.2 / int0 p3.3 / int1 p3.4 / t0 p3.5 / t1 p4.0 / txdc p0.3 / ad3 p0.2 / ad2 p0.1 / ad1 v aref v agnd p1.1 / an1 / int4 / cc1 p1.2 / an2 / int5 / cc2 p1.3 / an3 / int6 / cc3 p1.4 / an4 p0.0 / ad0 p1.0 / an0 / int3 / cc0 c505 c505c c505a c505ca
c505/c505c/c505a/c505ca data sheet 6 12.00 table 2 pin definitions and functions symbol pin number i/o *) function p1.0-p1.7 40-44,1-3 40 41 42 43 44 1 2 3 i/o port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 1 pins can be used for digital input/output or as analog inputs of the a/d converter. port 1 pins that have 1 ? s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. port 1 pins are assigned to be used as analog inputs via the register p1ana. as secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). the secondary functions are assigned to the pins of port 1 as follows: p1.0 / an0 / int3 / cc0 analog input channel 0 interrupt 3 input / capture/compare channel 0 i/o p1.1 / an1 / int4 / cc1 analog input channel 1/ interrupt 4 input / capture/compare channel 1 i/o p1.2 / an2 / int5 / cc2 analog input channel 2 / interrupt 5 input / capture/compare channel 2 i/o p1.3 / an3 / int6 / cc3 analog input channel 3 interrupt 6 input / capture/compare channel 3 i/o p1.4 / an4 analog input channel 4 p1.5 / an5 / t2ex analog input channel 5 / timer 2 external reload / trigger input p1.6 / an6 / clkout analog input channel 6 / system clock output p1.7 / an7 / t2 analog input channel 7 / counter 2 input port 1 is used for the low-order address byte during program verification of the c505 rom versions (i.e. c505(c)(a)-2r/ c505a-4r/c505ca-4r). *) i = input o= output
c505/c505c/c505a/c505ca data sheet 7 12.00 reset 4 i reset a high level on this pin for two machine cycle while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v dd . p3.0-p3.7 5, 7-13 5 7 8 9 10 11 12 13 i/o port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 3 pins that have 1 ? s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for txd and wr ). the secondary functions are assigned to the pins of port 3 as follows: p3.0 / rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 / txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 / int0 external interrupt 0 input / timer 0 gate control input p3.3 / int1 external interrupt 1 input / timer 1 gate control input p3.4 / t0 timer 0 counter input p3.5 / t1 timer 1 counter input p3.6 / wr wr control output; latches the data byte from port 0 into the external data memory p3.7 / rd rd control output; enables the external data memory *) i = input o= output table 2 pin definitions and functions (cont ? d) symbol pin number i/o *) function
c505/c505c/c505a/c505ca data sheet 8 12.00 p4.0 p4.1 6 28 i/o i/o port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. port 4 pins that have 1 ? s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. the output latch corresponding to the secondary function rxdc must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the two pins of port 4 as follows (c505c and c505ca only) : p4.0 / txdc transmitter output of can controller p4.1 / rxdc receiver input of can controller xtal2 14 o xtal2 output of the inverting oscillator amplifier. xtal1 15 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. to operate above a frequency of 16 mhz, a duty cycle of the etxernal clock signal of 50 % should be maintained. minimum and maximum high and low times as well as rise/ fall times specified in the ac characteristics must be observed. *) i = input o= output table 2 pin definitions and functions (cont ? d) symbol pin number i/o *) function
c505/c505c/c505a/c505ca data sheet 9 12.00 p2.0-p2.7 18-25 i/o port 2 is a an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1 ? s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup transistors when issuing 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register and uses only the internal pullup resistors. psen 26 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every three oscillator periods except during external data memory accesses. remains high during internal program execution. this pin should not be driven during reset operation. ale 27 o the address latch enable output is used for latching the low-byte of the address into external memory during normal operation. it is activated every three oscillator periods except during an external data memory access. when instructions are executed from internal rom or otp (ea =1) the ale generation can be disabled by bit eale in sfr syscon. ale should not be driven during reset operation. *) i = input o= output table 2 pin definitions and functions (cont ? d) symbol pin number i/o *) function
c505/c505c/c505a/c505ca data sheet 10 12.00 ea 29 i external access enable when held at high level, instructions are fetched from the internal program memory when the pc is less than 4000 h (c505(c)(a)-2r) or 8000 h (c505a-4r/c505ca-4r/c505a- 4e/c505ca-4e). when held at low level, the c505 fetches all instructions from external program memory. for the c505 romless versions (i.e. c505-l, c505c-l, c505a-l and c505ca-l) this pin must be tied low. for the rom protection version ea pin is latched during reset. p0.0-p0.7 37-30 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1 ? s written to them float, and in that state can be used as high-impendance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pullup transistors when issuing 1 ? s. port 0 also outputs the code bytes during program verification in the c505 rom versions. external pullup resistors are required during program verification. v aref 38 ? reference voltage for the a/d converter. v agnd 39 ? reference ground for the a/d converter. v ss 16 ? ground (0v) v dd 17 ? power supply (+5v) *) i = input o= output table 2 pin definitions and functions (cont ? d) symbol pin number i/o *) function
c505/c505c/c505a/c505ca data sheet 11 12.00 figure 4 block diagram of the c505/c505c/c505a/c505ca port 0 8-bit digit. i/o port 2 8-bit digit. i/o port 3 8-bit digit. i/o port 0 port 1 port 2 port 3 osc & timing cpu timer 0 timer 1 timer 2 usart xtal1 xtal2 reset ale psen ea vss v dd oscillator watchdog a/d converter 8-/10-bit 1) s&h mux v agnd v aref port 1 8-bit digit. i/o / 8-bit analog in 16k or 32k rom/ 256 byte xram 256 byte ram emulation support logic programmable watchdog timer full-can controller 256 byte reg./dat a interrupt unit 8 datapointers port 4 2-bit digit. i/o port 4 c505c/c505ca only. or 1k byte otp byte 1) 1) 1) please refer to table 1 for device specific configuration. baudrate generator
c505/c505c/c505a/c505ca data sheet 12 12.00 cpu the c505 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. with a 16 mhz crystal, 58% of the instructions are executed in 375 ns (20mhz: 300 ns). special function register psw (address d0 h ) reset value : 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag p parity flag set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
c505/c505c/c505a/c505ca data sheet 13 12.00 memory organization the c505 cpu manipulates operands in the following four address spaces: ? on-chip program memory :16k byte rom (c505(c)(a)-2r) or 32k byte rom (c505a-4r/c505ca-4r) or 32k byte otp (c505a-4e/c505ca-4e) ? totally up to 64k byte internal/external program memory ? up to 64 kbyte of external data memory ? 256 bytes of internal data memory ? internal xram data memory :256 byte (c505/c505c) 1k byte (c505a/c505ca) ? a 128 byte special function register area figure 5 illustrates the memory address spaces of the c505 versions. figure 5 c505 memory map memory map ext. int. (ea = 1) ext. data memory int. can contr. (256 byte) (ea = 0) ext. ffff h 8000 h 3fff / h 0000 h data memory ext. f700 h f6ff h 0000 h 00 h h 7f regs. function special ram internal ram internal h 80 h ff addr. indirect addr. direct alternatively "code space" "data space" "internal data space" mcb03632 xram internal ffff h 80 h ff h see table below for detailed data memory partitioning h 4000 / 7fff h device can area c505 c505c c505a c505ca f700 f7ff hh unused area f800 feff hh f700 feff hh ff00 ffff xram area hh "data space" f700 to ffff : hh f700 f7ff hh f800 fbff f700 fbff h h h h ff00 ffff hh fc00 ffff hh fc00 ffff hh unused area
c505/c505c/c505a/c505ca data sheet 14 12.00 reset and system clock the reset input is an active high input at pin reset. since the reset is synchronized internally, the reset pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. a pulldown resistor is internally connected to v ss to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v dd is applied by connecting the reset pin to v dd via a capacitor. figure 6 shows the possible reset circuitries. figure 6 reset circuitries reset + a) b) c) v dd + v dd v dd c505 c505c c505a c505ca reset c505 c505c c505a c505ca & reset c505 c505c c505a c505ca
c505/c505c/c505a/c505ca data sheet 15 12.00 figure 7 shows the recommended oscillator circuits for crystal and external clock operation. figure 7 recommended oscillator circuitries xtal1 xtal2 c = 20 pf 10pf for crystal operation c c 2-20 mhz c = 20pf 10pf for crystal operation external clock signal v dd n.c. xtal2 xtal1 c505 c505c c505a c505ca c505 c505c c505a c505ca
c505/c505c/c505a/c505ca data sheet 16 12.00 multiple datapointers as a functional enhancement to the standard 8051 architecture, the c505 contains eight 16-bit datapointers instead of only one datapointer. the instruction set uses just one of these datapointers at a time. the selection of the actual datapointer is done in the special function regsiter dpsel. figure 8 illustrates the datapointer addressing mechanism. figure 8 external data memory addressing using multiple datapointers dph(83 ) dpl(82 ) dptr0 dptr7 .0 .1 .2 - - - - - dpsel(92 ) dpsel selected data- pointer .2 .1 .0 dptr 0 0 0 0 0 0 1 dptr 1 0 1 0 dptr 2 0 1 1 dptr 3 1 0 0 dptr 4 1 0 1 dptr 5 1 1 0 dptr 6 1 1 1 dptr 7 mcd00779 external data memory h hh
c505/c505c/c505a/c505ca data sheet 17 12.00 enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip rom based programs is possible, too. each production chip has built-in logic for the supprt of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology tm 1) , which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500 microcontrollers. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 9 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. 1) ? enhanced hooks technology ? is a trademark and patent of metalink corporation licensed to infineon technologies. mcs02647 syscon pcon tcon reset ea psen ale port 0 port 2 i/o ports optional port 3 port 1 c500 mcu interface circuit enhanced hooks rport 0 rport 2 rtcon rpcon rsyscon tea tale tpsen eh-ic target system interface ice-system interface to emulation hardware
c505/c505c/c505a/c505ca data sheet 18 12.00 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function register area consists of two portions : the standard special function register area and the mapped special function register area. five special function register of the c505 (pcon1,p1ana, vr0, vr1, vr2) are located in the mapped special function register area. for accessing the mapped special function register area, bit rmap in special function register syscon must be set. all other special function registers are located in the standard special function register area which is accessed when rmap is cleared ( ? 0 ? ). the registers and data locations of the can controller (can-sfrs) are located in the external data memory area at addresses f700 h to f7ff h .. special function register syscon (address b1 h ) reset value : xx100x01 b (c505ca only) reset value : xx100001 b as long as bit rmap is set, mapped special function register area can be accessed. this bit is not cleared by hardware automatically. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set respectively by software. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , ..., f8 h , ff h ) are bitaddressable. the 52 special function registers (sfrs) in the standard and mapped sfr area include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. the sfrs of the c505 are listed in table 3 and table 4 . in table 3 they are organized in groups which refer to the functional blocks of the c505. the can-sfrs (applicable for the c505c and c505ca only) are also included in table 3 . table 4 illustrates the contents of the sfrs in numeric order of their addresses. table 5 list the can-sfrs in numeric order of their addresses. bit function rmap special function register map bit rmap = 0 : the access to the non-mapped (standard) special function register area is enabled. rmap = 1 : the access to the mapped special function register area is enabled. cswo can controller switch-off bit cswo = 0 : can controller is enabled (default after reset). cswo = 1 : can controller is switched off. 76543210 eale rmap cmod b1 h syscon bit no. msb lsb cswo xmap1 ?? xmap0 the functions of the shaded bits are not described here. 1) 1) this bit is only available in the c505ca.
c505/c505c/c505a/c505ca data sheet 19 12.00 table 3 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl dpsel psw sp syscon 2) vr0 4) vr1 4) vr2 4) accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer system control register version register 0 version register 1 version register 2 e0 h 1) f0 h 1) 83 h 82 h 92 h d0 h 1) 81 h b1 h fc h fd h fe h 00 h 00 h 00 h 00 h xxxxx000 b 3) 00 h 07 h xx100x01 b 3) 6) xx100001 b 3) 7) c5 h 05 h 5) a/d- converter adcon0 2) adcon1 addat adst addath addatl p1ana 2) 4) a/d converter control register 0 a/d converter control register 1 a/d converter data reg. (c505/c505c) a/d converter start reg. (c505/c505c) a/d converter high byte data register (c505a/c505ca) a/d converter low byte data register (c505a/c505ca) port 1 analog input selection register d8 h 1) dc h d9 h da h d9 h da h 90 h 00x00000 b 3) 01xxx000 b 3) 00 h xx h 3) 00 h 00xxxxxx b 3) ff h interrupt system ien0 2) ien1 2) ip0 2) ip1 tcon 2) t2con 2) scon 2) ircon interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 timer control register timer 2 control register serial channel control register interrupt request control register a8 h 1) b8 h 1) a9 h b9 h 88 h 1) c8 h 1) 98 h 1) c0 h 1) 00 h 00 h 00 h xx000000 b 3) 00 h 00x00000 b 00 h 00 h xram xpage syscon 2) page address register for extended on-chip xram and can controller system control register 91 h b1 h 00 h xx100x01 b 3) 6) xx100001 b 3) 7) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ? x ? means that the value is undefined and the location is reserved 4) this sfr is a mapped sfr. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the content of this sfr varies with the actual step of the c505 (eg. 01 h for the first step) 6) c505 / c505a/c505c only 7) c505ca only
c505/c505c/c505a/c505ca data sheet 20 12.00 ports p0 p1 p1ana 2) 4) p2 p3 p4 port 0 port 1 port 1 analog input selection register port 2 port 3 port 4 80 h 1) 90 h 1) 90 h 1) a0 h 1) b0 h 1) e8h 1) ff h ff h ff h ff h ff h xxxxxx11 b serial channel adcon0 2) pcon 2) sbuf scon srell srelh a/d converter control register 0 power control register serial channel buffer register serial channel control register serial channel reload register, low byte serial channel reload register, high byte d8 h 1) 87 h 99 h 98 h 1) aa h ba h 00x00000 b 3) 00 h xx h 3) 00 h d9 h xxxxxx11 b 3) timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h compare/ capture unit / timer 2 ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con ien0 2) ien1 2) comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte reload register high byte reload register low byte timer 2, high byte timer 2, low byte timer 2 control register interrupt enable register 0 interrupt enable register 1 c1 h c3 h c5 h c7 h c2 h c4 h c6 h cb h ca h cd h cc h c8 h 1) a8 h 1) b8 h 1) 00 h 3) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00x00000 b 3) 00 h 00 h watchdog wdtrel ien0 2) ien1 2) ip0 2) watchdog timer reload register interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 86 h a8 h 1) b8 h 1) a9 h 00 h 00 h 00 h 00 h pow. save modes pcon 2) pcon1 4) power control register power control register 1 87 h 88 h 1) 00 h 0xx0xxxx b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ? x ? means that the value is undefined and the location is reserved 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 3 special function registers - functional blocks (cont ? d) block symbol name address contents after reset
c505/c505c/c505a/c505ca data sheet 21 12.00 can controller (c505c/ c505ca only) cr sr ir btr0 btr1 gms0 gms1 ugml0 ugml1 lgml0 lgml1 umlm0 umlm1 lmlm0 lmlm1 mcr0 mcr1 uar0 uar1 lar0 lar1 mcfg db0 db1 db2 db3 db4 db5 db6 db7 control register status register interrupt register bit timing register low bit timing register high global mask short register low global mask short register high upper global mask long register low upper global mask long register high lower global mask long register low lower global mask long register high upper mask of last message register low upper mask of last message register high lower mask of last message register low lower mask of last message register high message object registers : message control register low message control register high upper arbitration register low upper arbitration register high lower arbitration register low lower arbitration register high message configuration register message data byte 0 message data byte 1 message data byte 2 message data byte 3 message data byte 4 message data byte 5 message data byte 6 message data byte 7 f700 h f701 h f702 h f704 h f705 h f706 h f707 h f708 h f709 h f70a h f70b h f70c h f70d h f70e h f70f h f7n0 h 5) f7n1 h 5) f7n2 h 5) f7n3 h 5) f7n4 h 5) f7n5 h 5) f7n6 h 5) f7n7 h 5) f7n8 h 5) f7n9 h 5) f7na h 5) f7nb h 5) f7nc h 5) f7nd h 5) f7ne h 5) 01 h xx h 3) xx h 3) uu h 3) 0uuuuuuu b 3) uu h 3) uuu11111 b 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uu h 3) uu h 3) uu h 3) uu h 3) uu h 3) uuuuu000 b 3) uuuuuu00 b 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ? x ? means that the value is undefined and the location is reserved. ? u ? means that the value is unchanged by a reset operation. ? u ? values are undefined (as ? x ? ) after a power-on reset operation 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the notation ? n ? (n= 1 to f) in the message object address definition defines the number of the related message object. table 3 special function registers - functional blocks (cont ? d) block symbol name address contents after reset
c505/c505c/c505a/c505ca data sheet 22 12.00 table 4 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 3) pcon1 0xx0- xxxx b ewpd ? ? ws ? ? ? ? 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex .4 int6 int5 int4 .int 3 90 h 3) p1ana ff h ean7 ean6 ean5 ean4 ean3 ean2 ean1 ean0 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 92 h dpsel xxxx- x000 b ????? .2 .1 .0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h ea wdt et2 es et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0 aa h srell d9 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
c505/c505c/c505a/c505ca data sheet 23 12.00 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b1 h syscon 3) xx10- 0x01 b ?? eale rmap cmod ? xmap1 xmap0 b1 h syscon 4) xx10- 0001 b ?? eale rmap cmod cswo xmap1 xmap0 b8 h 2) ien1 00 h exen2 swdt ex6 ex5 ex4 ex3 ecan eadc b9 h ip1 xx00- 0000 b ?? .5 .4 .3 .2 .1 .0 ba h srelh xxxx- xx11 b ?????? .1 .0 c0 h 2) ircon 00 h exf2 tf2 iex6 iex5 iex4 iex3 swi iadc c1 h ccen 00 h coca h3 cocal 3 coca h2 cocal 2 coca h1 cocal 1 coca h0 cocal 0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00x0- 0000 b t2ps i3fr ? t2r1 t2r0 t2cm t2i1 t2i0 ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d8 h 2) adcon0 00x0- 0000 b bd clk ? bsy adm mx2 mx1 mx0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) c505 /c505c/c505a only 4) c505ca only table 4 contents of the sfrs, sfrs in numeric order of their addresses (cont ? d) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c505/c505c/c505a/c505ca data sheet 24 12.00 d9 h addat 6) 00 h .7 .6 .5 .4 .3 .2 .1 .0 d9 h addath 7) 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h adst 6) xxxx- xxxx b ???????? da h addatl 7) 00xx- xxxx b .1 .0 ?????? dc h adcon1 01xx- x000 b adcl1 adcl0 ??? mx2 mx1 mx0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 xxxx- xx11 b ? ? ? ? ? ? rxdc txdc f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 fc h 3)4) vr0 c5 h 11000101 fd h 3)4) vr1 05 h 00000101 fe h 3)4) vr2 5) 01 h 8) 12 h 9) 33 h 10) .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 4) these are read-only registers 5) the content of this sfr varies with the actual of the step c505 (eg. 01 h or 11 h or 21 h for the first step) 6) c505 / c505c only 7) c505a / c505ca only 8) c505 / c505c ab step only 9) c505a-4e / c505ca-4e ba step only (11 h for the aa step) 10) c505a-4r / c505ca-4r bb step only (32 h for the ba step) table 4 contents of the sfrs, sfrs in numeric order of their addresses (cont ? d) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c505/c505c/c505a/c505ca data sheet 25 12.00 table 5 contents of the can registers in numeric order of their addresses (c505c/c505ca only) addr. n=1-f h 1) register content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f700 h cr 01 h test cce 0 0 eie sie ie init f701 h sr xx h boff ewrn ? rxok txok lec2 lec1 lec0 f702 h ir xx h intid f704 h btr0 uu h sjw brp f705 h btr1 0uuu. uuuu b 0 tseg2 tseg1 f706 h gms0 uu h id28-21 f707 h gms1 uuu1. 1111 b id20-18 11111 f708 h ugml0 uu h id28-21 f709 h ugml1 uu h id20-13 f70a h lgml0 uu h id12-5 f70b h lgml1 uuuu. u000 b id4-0 000 f70c h umlm0 uu h id28-21 f70d h umlm1 uu h id20-18 id17-13 f70e h lmlm0 uu h id12-5 f70f h lmlm1 uuuu. u000 b id4-0 000 f7n0 h mcr0 uu h msgval txie rxie intpnd f7n1 h mcr1 uu h rmtpnd txrq msglst cpuupd newdat f7n2 h uar0 uu h id28-21 f7n3 h uar1 uu h id20-18 id17-13 f7n4 h lar0 uu h id12-5 f7n5 h lar1 uuuu. u000 b id4-0 000 1) the notation ? n ? (n= 1 to f) in the address definition defines the number of the related message object. 2) ? x ? means that the value is undefined and the location is reserved. ? u ? means that the value is unchanged by a reset operation. ? u ? values are undefined (as ? x ? ) after a power-on reset operation
c505/c505c/c505a/c505ca data sheet 26 12.00 f7n6 h mcfg uuuu. uu00 b dlc dir xtd 0 0 f7n7 h db0 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n8 h db1 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n9 h db2 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7na h db3 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nb h db4 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nc h db5 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nd h db6 xx h .7 .6 .5 .4 .3 .2 .1 .0 f7ne h db7 xx h .7 .6 .5 .4 .3 .2 .1 .0 1) the notation ? n ? (n= 1 to f) in the address definition defines the number of the related message object. 2) ? x ? means that the value is undefined and the location is reserved. ? u ? means that the value is unchanged by a reset operation. ? u ? values are undefined (as ? x ? ) after a power-on reset operation table 5 contents of the can registers in numeric order of their addresses (cont ? d) (c505c/c505ca only) addr. n=1-f h 1) register content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c505/c505c/c505a/c505ca data sheet 27 12.00 i/o ports the c505 has four 8-bit i/o ports and one 2-bit i/o port. port 0 is an open-drain bidirectional i/o port, while ports 1 to 4 are quasi-bidirectional i/o ports with internal pullup resistors. that means, when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally pulled low. port 0 will float when configured as input. the output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. in this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. port 2 outputs the high byte of the external memory address when the address is 16 bits wide. otherwise, the port 2 pins continue emitting the p2 sfr contents. in this function, port 0 is not an open-drain port, but uses a strong internal pullup fet . port 4 is 2-bit i/o port with can controller specific alternate functions. the eight analog input lines are realized as mixed digital/analog inputs. the 8 analog inputs, an0-an7, are located at the port 1 pins p1.0 to p1.7. after reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. the analog function of a specific port 1 pin is enabled by bits in the sfr p1ana. writing a 0 to a bit position of p1ana assigns the corresponding pin to operate as analog input. note : p1ana is a mapped sfr and can be only accessed if bit rmap in sfr syscon is set.
c505/c505c/c505a/c505ca data sheet 28 12.00 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 6 : in the ? timer ? function (c/t = ? 0 ? ) the register is incremented every machine cycle. therefore the count rate is f osc /6. in the ? counter ? function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /12. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 10 illustrates the input clock logic. figure 10 timer/counter 0 and 1 input clock logic table 6 timer/counter 0 and 1 operating modes mode description tmod input clock m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 f osc /6x32 f osc /12x32 1 16-bit timer/counter 0 1 f osc /6 f osc /12 2 8-bit timer/counter with 8-bit autoreload 10 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops 11 mcs03117 1 & osc c/t = 0 c/t = 1 control =1 6 tr1 p3.5/t1 (tmod) p3.2/int0 f timer 0/1 input clock osc /6 p3.4/t0 tr0 gate p3.3/int1 _ <
c505/c505c/c505a/c505ca data sheet 29 12.00 timer/counter 2 with compare/capture/reload the timer 2 of the c505 provides additional compare/capture/reload features. which allow the selection of the following operating modes: ? compare : up to 4 pwm signals with 16-bit/300 ns resolution (@ 20 mhz clock) ? capture : up to 4 high speed capture inputs with 300 ns resolution ? reload : modulation of timer 2 cycle time the block diagram in figure 11 shows the general configuration of timer 2 with the additional compare/capture/reload registers. the i/o pins which can used for timer 2 control are located as multifunctional port functions at port 1. figure 11 timer 2 block diagram mcb02730 comparator ccl3/cch3 capture input/ output control p1.0/ int3/ cc0 cc1 int4/ p1.1/ cc2 int5/ p1.2/ cc3 int6/ p1.2/ ccl2/cch2 comparator ccl1/cch1 comparator crcl/crch comparator bit 16 16 bit 16 bit 16 bit osc 6 12 f osc t2ps sync. p1.7/ t2 t2ex p1.5/ sync. & t2i1 t2i0 timer 2 th2 tl2 tf2 reload exen2 reload 1 exf2 interrupt request compare _ <
c505/c505c/c505a/c505ca data sheet 30 12.00 timer 2 operating modes the timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. a roll-over of the count value in tl2/th2 from all 1 ? s to all 0 ? s sets the timer overflow flag tf2 in sfr ircon, which can generate an interrupt. the bits in register t2con are used to control the timer 2 operation. timer mode : in timer function, the count rate is derived from the oscillator frequency. a prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. gated timer mode : in gated timer function, the external input pin t2 (p1.7) functions as a gate to the input of timer 2. lf t2 is high, the internal clock input is gated to the timer. t2 = 0 stops the counting procedure. this facilitates pulse width measurements. the external gate signal is sampled once every machine cycle. event counter mode : in the event counter function. the timer 2 is incremented in response to a 1- to-0 transition at its corresponding external input pin t2 (p1.7). in this function, the external input is sampled every machine cycle. since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. reload of timer 2 : two reload modes are selectable: in mode 0, when timer 2 rolls over from all 1 ? s to all 0 ? s, it not only sets tf2 but also causes the timer 2 registers to be loaded with the 16-bit value in the crc register, which is preset by software. in mode 1, a 16-bit reload from the crc register is caused by a negative transition at the correspon- ding input pin p1.5/t2ex. this transition will also set flag exf2 if bit exen2 in sfr ien1 has been set.
c505/c505c/c505a/c505ca data sheet 31 12.00 timer 2 compare modes the compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. compare mode 0 in compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. as long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. figure 12 shows a functional diagram of a port circuit when used in compare mode 0. the port latch is directly controlled by the timer overflow and compare match signals. the input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. figure 12 port latch in compare mode 0 mcs02661 latch port q q clk d port pin read pin dd v read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match s r overflow timer 16 bit bit 16
c505/c505c/c505a/c505ca data sheet 32 12.00 compare mode 1 if compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. in compare mode 1 (see figure 13 ) the port circuit consists of two separate latches. one latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. figure 13 compare function in compare mode 1 timer 2 capture modes each of the compare/capture registers cc1 to cc3 and the crc register can be used to latch the current 16-bit value of the timer 2 registers tl2 and th2. two different modes are provided for this function. in mode 0 , the external event causing a capture is : ? for cc registers 1 to 3: a positive transition at pins cc1 to cc3 of port 1 ? for the crc register: a positive or negative transition at the corresponding pin, depending on the status of the bit i3fr in sfr t2con. in mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. the write-to-register signal (e.g. write-to-crcl) is used to initiate a capture. the timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. in this mode no interrupt request will be generated. mcs02662 latch port q q clk d read pin dd v d clk q shadow latch read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match pin port 16 bit 16 bit
c505/c505c/c505a/c505ca data sheet 33 12.00 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 7 . for clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. in the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in figure 14 to the serial interface which - there divided by 16 - results in the actual "baud rate". further, the abbrevation f osc refers to the oscillator frequency (crystal or external clock operation). the variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a decdicated baud rate generator (see figure 14 ). table 7 usart operating modes mode scon description sm0 sm1 0 0 0 shift register mode, fixed baud rate serial data enters and exits through r d; t d outputs the shift clock; 8-bit are transmitted/received (lsb first) 1 0 1 8-bit uart, variable baud rate 10 bits are transmitted (through t d) or received (at r d) 2 1 0 9-bit uart, fixed baud rate 11 bits are transmitted (through t d) or received (at r d) 3 1 1 9-bit uart, variable baud rate like mode 2
c505/c505c/c505a/c505ca data sheet 34 12.00 figure 14 block diagram of baud rate generation for the serial interface table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits bd and smod. table 8 serial interface - baud rate dependencies serial interface operating modes active control bits baud rate calculation bd smod mode 0 (shift register) ?? f osc / 6 mode 1 (8-bit uart) mode 3 (9-bit uart) 0 x controlled by timer 1 overflow : (2 smod timer 1 overflow rate) / 32 1 x controlled by baud rate generator (2 smod f osc ) / (32 baud rate generator overflow rate) mode 2 (9-bit uart) ? 0 1 f osc / 32 f osc / 16 mcs02733 rate f osc (smod) baud clock pcon.7 2 (sm0/ sm1) scon.7 scon.6 only one mode can be selected adcon0.7 (bd) 0 1 0 1 baud rate generator (srelh srell) timer 1 mode 2 mode 0 note: the switch configuration shows the reset state. mode 3 mode 1 overflow 6
c505/c505c/c505a/c505ca data sheet 35 12.00 can controller (c505c and c505ca only) the on-chip can controller, compliant to version 2.0b, is the functional heart which provides all resources that are required to run the standard can protocol (11-bit identifiers) as well as the extended can protocol (29-bit identifiers). it provides a sophisticated object layer to relieve the cpu of as much overhead as possible when controlling many different message objects (up to 15). this includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. in order to implement the physical layer, external components have to be connected to the c505c/c505ca. the internal bus interface connects the on-chip can controller to the internal bus of the microcontroller. the registers and data locations of the can interface are mapped to a specific 256 byte wide address range of the external data memory area (f700 h to f7ff h ) and can be accessed using movx instructions. figure 15 shows a block diagram of the on-chip can controller. the tx/rx shift register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the intelligent memory. the bit stream processor (bsp) is a sequencer controlling the sequential data stream between the tx/rx shift register, the crc register, and the bus line. the bsp also controls the eml and the parallel data stream between the tx/rx shift register and the intelligent memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the can protocol. note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the bsp. the cyclic redundancy check register (crc) generates the cyclic redundancy check code to be transmitted after the data bytes and checks the crc code of incoming messages. this is done by dividing the data stream by the code generator polynomial. the error management logic (eml) is responsible for the fault confinement of the can device. its counters, the receive error counter and the transmit error counter, are incremented and decremented by commands from the bit stream processor. according to the values of the error counters, the can controller is set into the states error active , error passive and busoff. the bit timing logic (btl) monitors the busline input rxdc and handles the busline related bit timing according to the can protocol. the btl synchronizes on a recessive to dominant busline transition at start of frame (hard synchronization) and on any further recessive to dominant busline transition, if the can controller itself does not transmit a dominant bit (resynchronization). the btl also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the sample point in the bit time. the programming of the btl depends on the baudrate and on external physical delay times. the intelligent memory (cam/ram array) provides storage for up to 15 message objects of maximum 8 data bytes length. each of these objects has a unique identifier and its own set of control and status bits. after the initial configuration, the intelligent memory can handle the reception and transmission of data without further microcontroller actions.
c505/c505c/c505a/c505ca data sheet 36 12.00 figure 15 can controller block diagram mcb02736 bit timing logic timing generator btl-configuration crc gen./check tx/rx shift register txdc rxdc intelligent interrupt register memory processor register status stream bit error logic management messages handlers control status + to internal bus clocks control messages (to all)
c505/c505c/c505a/c505ca data sheet 37 12.00 can controller software initialization the very first step of the initialization is the can controller input clock selection. a divide-by-2 prescaler is enabled by default after reset ( figure 16 ). setting bit cmod (syscon.3) disables the prescaler. the purpose of the prescaler selection is: ? to ensure that the can controller is operable when f osc is over 10 mhz (bit cmod =0) ? to achieve the maximum can baudrate of 1 mbaud when f osc is 8 mhz (bit cmod=1) figure 16 can controller input clock selection note : the switch configuration shows the reset state of bit cmod. syscon.3 0 1 (cmod) mcs03296 2 f osc full-can module can f condition: cmod = 0, when > 10 mhz osc f frequency (mhz) cmod (syscon.3) brp (btr0.0-5) can baudrate (mbaud/sec) f osc f can 8 8 1 000000 b 1 8 4 0 000000 b 0.5 16 8 0 000000 b 1
c505/c505c/c505a/c505ca data sheet 38 12.00 8-bit a/d converter (c505 and c505c only) the c505/c505c includes a high performance / high speed 8-bit a/d converter (adc) with 8 analog input channels. it operates with a successive approximation technique and provides the following features: ? 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs ? 8-bit resolution ? internal start-of-conversion trigger ? interrupt request generation after each conversion ? single or continuous conversion mode the 8-bit adc uses two clock signals for operation : the conversion clock f adc (=1/t adc ) and the input clock f in (1/t in ). f adc is derived from the c505 system clock f osc which is applied at the xtal pins via the adc clock prescaler as shown in figure 17 . the input clock is equal to f osc . the conversion clock f adc is limited to a maximum frequency of 1.25 mhz. therefore, the adc clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 1.25 mhz. the prescaler ratio is selected by the bits adcl1 and adcl0 of sfr adcon1. figure 17 8-bit a/d converter clock selection mcs03299 f osc mux clock prescaler conversion clock input clock f adc in f adcl1 a / d converter condition: adc max f < 1.25 mhz in f = f osc = clp 1 32 8 4 16 adcl0 mcu system clock rate (f osc ) f in [mhz] prescaler ratio f adc [mhz] adcl1 adcl0 2 mhz 2 4 0.5 0 0 5 mhz 5 4 1.25 0 0 6 mhz 6 8 0.75 0 1 10 mhz 10 8 1.25 0 1 12 mhz 12 16 0.75 1 0 16 mhz 16 16110 20 mhz 20 16 1.25 1 0
c505/c505c/c505a/c505ca data sheet 39 12.00 figure 18 block diagram of the 8-bit a/d converter adc shaded bit locations are not used in adc-functions. f agnd aref osc v v port 1 conversion prescaler clock mux f conversion clock input clock f in s&h adcon1 (dc ) adcon0 (d8 ) adcl1 h adcl0 h ircon (c0 ) p1ana (90 ) ean7 ean6 h h bsy ean5 ean4 ien1 (b8 ) h write to adst mcb03298 (da ) adst conversion converter a / d continuous mode single / start of msb .6 .5 .4 lsb .2 .3 .1 h (d9 ) addat bus internal h adm mx2 mx2 ean3 ean2 mx1 mx1 mx0 mx0 ean1 iadc ean0 eadc bus internal clk bd swi iex3 iex4 iex5 iex6 tf2 exf2 ecan ex3 ex4 ex5 ex6 swdt exen2
c505/c505c/c505a/c505ca data sheet 40 12.00 10-bit a/d converter (c505a and c505ca only) the c505a/c505ca includes a high performance / high speed 10-bit a/d-converter (adc) with 8 analog input channels. it operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the a/d converter provides the following features: ? 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs ? 10-bit resolution ? single or continuous conversion mode ? internal start-of-conversion trigger capability ? interrupt request generation after each conversion ? using successive approximation conversion technique via a capacitor array ? built-in hidden calibration of offset and linearity errors the 10-bit adc uses two clock signals for operation : the conversion clock f adc (=1/t adc ) and the input clock f in (=1/t in ). f adc is derived from the c505 system clock f osc which is applied at the xtal pins. the input clock f in is equal to f osc the conversion f adc clock is limited to a maximum frequency of 2 mhz. therefore, the adc clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 mhz. the prescaler ratio is selected by the bits adcl1 and adcl0 of sfr adcon1. figure 19 10-bit a/d converter clock selection mcs03635 f osc mux clock prescaler conversion clock input clock f adc in f adcl1 a / d converter condition: adc max f < 2 mhz in f = f osc = clp 1 32 8 4 16 adcl0 mcu system clock rate (f osc ) f in [mhz] prescaler ratio f adc [mhz] adcl1 adcl0 2 mhz 2 4 0.5 0 0 6 mhz 6 4 1.5 0 0 8 mhz 8 4200 12 mhz 12 8 1.5 0 1 16 mhz 16 8201 20 mhz 20 16 1.25 1 0
c505/c505c/c505a/c505ca data sheet 41 12.00 figure 20 block diagram of the 10-bit a/d converter adc shaded bit locations are not used in adc-functions. f agnd aref osc v v port 1 conversion prescaler clock mux f conversion clock input clock f in s&h adcon1 (dc ) adcon0 (d8 ) adcl1 h adcl0 h ircon (c0 ) p1ana (90 ) ean7 ean6 h h bsy ean5 ean4 ien1 (b8 ) h write to addatl mcb03636 (da ) adst conversion converter a / d continuous mode single / start of msb .6 .5 .4 lsb .2 .3 .1 h (d9 ) addat bus internal h adm mx2 mx2 ean3 ean2 mx1 mx1 mx0 mx0 ean1 iadc ean0 eadc bus internal .8 .7 iex5 ex5 exf2 exen2 bd clk tf2 swdt iex6 ex6 iex4 ex4 iex3 ex3 swi ecan addath (d9 h ) addatl (da h )
c505/c505c/c505a/c505ca data sheet 42 12.00 interrupt system the c505 provides 12 interrupt vectors with four priority levels. five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, a/d converter). one interrupt can be generated by the can controller (c505c and c505ca only) or by a software setting and in this case the interrupt vector is the same. six interrupts may be triggered externally (p3.2/ int0 , p3.3/int1 , p1.0/an0/int3 /cc0, p1.1/an1/int4/cc1, p1.2/an2/int5/cc2, p1.3/an3/int6/ cc3). additionally, the p1.5/an5/t2ex can trigger an interrupt. the wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at either pin p3.2/int0 or the pin p4.1/rxdc. figure 21 to figure 23 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections. table 9 lists all interrupt sources with their request flags and interrupt vector addresses. table 9 interrupt source and vectors interrupt source interrupt vector address interrupt request flags external interrupt 0 0003 h ie0 timer 0 overflow 000b h tf0 external interrupt 1 0013 h ie1 timer 1 overflow 001b h tf1 serial channel 0023 h ri / ti timer 2 overflow / ext. reload 002b h tf2 / exf2 a/d converter 0043 h iadc can controller / software interrupt 004b h ? / swi external interrupt 3 0053 h iex3 external interrupt 4 005b h iex4 external interrupt 5 0063 h iex5 external interrupt 6 006b h iex6 wake-up from power-down mode 007b h ?
c505/c505c/c505a/c505ca data sheet 43 12.00 figure 21 interrupt structure, overview part 1 note: each of the 15 can controller message objects (c505c and c505ca only), shown in the shaded area of figure 21 provides the bits/flags. ea et0 ip1.1 ip0.1 iadc eadc ex0 ip1.0 ip0.0 ie0 ien0.0 tcon.1 0003 h h 0043 h 000b h 004b ien1.0 ircon.0 ien1.1 ien0.1 a / d converter ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03303 it0 tcon.5 tf0 tcon.0 p3.2 / int0 overflow timer 0 bit addressable request flag is cleared by hardware >1 ircon.1 c505c and c505ca only ecan swi mcr0.5 / 4 mcr0.3 / 2 receive message transmit message error status mcr0.0 / 1 intpnd cr.1 cr.3 rxie txie >1 eie cr.2 sie >1 ie can controller interrupt sources ecan
c505/c505c/c505a/c505ca data sheet 44 12.00 figure 22 interrupt structure, overview part 2 ea et1 iex3 ex3 ex1 ip1.2 ip0.2 ie1 ien0.2 tcon.3 0013 h h 0053 h 001b h 005b ien1.2 ircon.2 ien1.3 ien0.3 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03304 it1 tcon.7 tf1 tcon.2 p3.3 / int1 overflow timer 1 bit addressable request flag is cleared by hardware an0 / int3 / t2con.6 i3fr p1.0 / cc0 ip0.3 ip1.3 ircon.3 iex4 an1 / p1.1 / int4 / cc1 ex4
c505/c505c/c505a/c505ca data sheet 45 12.00 figure 23 interrupt structure, overview part 3 ea et2 iex5 ex5 es ip1.4 ip0.4 ri ien0.4 scon.0 0023 h h 0063 h 002b h 006b ien1.4 ircon.4 ien1.5 ien0.5 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03305 usart overflow timer 2 bit addressable request flag is cleared by hardware ip0.5 ip1.5 ircon.5 iex6 an2 / p1.2 / int5 / cc2 ex6 ti scon.1 >1 cc3 int6 / p1.3 / ircon.7 exf2 tf2 ircon.6 >1 ien1.7 exen2 an5 / t2ex p1.5 /
c505/c505c/c505a/c505ca data sheet 46 12.00 fail save mechanisms the c505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : ? a programmable watchdog timer (wdt), with variable time-out period from 192 s up to approx. 393.2 ms at 16 mhz (314.5 ms at 20 mhz). ? an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. the watchdog timer in the c505 is a 15-bit timer, which is incremented by a count rate of f osc /12 upto f osc /192. the system clock of the c505 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. for programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. figure 24 shows the block diagram of the watchdog timer unit. figure 24 block diagram of the programmable watchdog timer the watchdog timer can be started by software (bit swdt in sfr ien1) but it cannot be stopped during active mode of the device. if the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. for refreshing of the watchdog timer the content of the sfr wdtrel is transfered to the upper 7-bit of the watchdog timer. the refresh sequence consists of two consequtive instructions which set the bits wdt and swdt each. the reset cause (external reset or reset caused by the watchdog) can be examined by software (flag wdts). it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. mcb03306 ip0 (a9 ) h osc f wdts 2 16 14 07 8 wdtl wdth / 6 external hw reset control logic ien0 (a8 ) h ien1 (b8 ) h 6 70 wdt reset - request wdtpsel wdtrel (86 ) h wdt swdt owds
c505/c505c/c505a/c505ca data sheet 47 12.00 oscillator watchdog the oscillator watchdog unit serves for three functions: ? monitoring of the on-chip oscillator's function the watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the rc oscillator), the part, in order to allow the oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog reset is released and the part starts program execution from address 0000 h again. ? fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. ? control of external wake-up from software power-down mode when the power-down mode is left by a low level at the p3.2/int0 pin or the p4.1/rxdc pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. in the power-down mode the rc oscillator and the on-chip oscillator are stopped. both oscillators are started again when power-down mode is released. when the on-chip oscillator has a higher frequency than the rc oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
c505/c505c/c505a/c505ca data sheet 48 12.00 figure 25 functional block diagram of the oscillator watchdog int. clock xtal2 xtal1 owds mcb03308 ip0 (a9 ) h 3 mhz f rc delay 1 f 2 f 2 f 1 f < p4.1 / rxdc start / stop start / stop mode activated power - down power-down mode wake - up interrupt internal reset 10 p3.2 / int0 control ws (pcon1.4) (pcon1.7) ewpd >1 frequency comparator rc on-chip oscillator logic oscillator logic control
c505/c505c/c505a/c505ca data sheet 49 12.00 power saving modes the c505 provides two basic power saving modes, the idle mode and the power down mode. additionally, a slow down mode is available. this power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. ? idle mode in the idle mode the main oscillator of the c505 continues to run, but the cpu is gated off from the clock signal. all peripheral units are further provided with the clock. the cpu status is preserved in its entirety. the idle mode can be terminated by any enabled interrupt of a peripheral unit or by a hardware reset. ? power down mode the operation of the c505 is completely stopped and the oscillator is turned off. this mode is used to save the contents of the internal ram with a very low standby current. power down mode is entered by software and can be left by reset or by a short low pulse at pin p3.2/ int0 .or p4.1/rxdc. ? slow down mode the controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. this slows down all parts of the controller, the cpu and all peripherals, to 1/32-th of their normal operating frequency. slowing down the frequency significantly reduces power consumption. in the power down mode of operation, v dd can be reduced to minimize power consumption. it must be ensured, however, that v dd is not reduced before the power down mode is invoked, and that v dd is restored to its normal operating level, before the power down mode is terminated. table 10 gives a general overview of the entry and exit procedures of the power saving modes. table 10 power saving modes overview mode entering (instruction example) leaving by remarks idle mode orl pcon, #01h orl pcon, #20h ocurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock hardware reset power down mode orl pcon, #02h orl pcon, #40h hardware reset oscillator is stopped; contents of on-chip ram and sfr ? s are maintained; short low pulse at pin p3.2/int0 or p4.1/rxdc slow down mode orl pcon,#10h anl pcon,#0efh or hardware reset oscillator frequency is reduced to 1/32 of its nominal frequency
c505/c505c/c505a/c505ca data sheet 50 12.00 otp memory operation (c505a-4e and c505ca-4e only) the c505a-4e/c505ca-4e contains a 32k byte one-time programmable (otp) program memory. with the c505a-4e/c505ca-4e fast programming cycles are achieved (1 byte in 100 sec). also several levels of otp memory protection can be selected. for programming of the device, the c505a-4e/c505ca-4e must be put into the programming mode. this typically is done not in-system but in a special programming hardware. in the programming mode the c505a-4e/c505ca-4e operates as a slave device similar as an eprom standalone memory device and must be controlled with address/data information, control lines, and an external 11.5v programming voltage. figure 26 shows the pins of the c505a-4e/c505ca-4e which are required for controlling of the otp programming mode. figure 26 programming mode configuration port 0 d0-d7 v dd v ss c505a-4e c505ca-4e prog a0-a7 / port 2 ea /v pp pmsel0 psel reset psen pmsel1 prd a8-a14 pale xtal1 xtal2
c505/c505c/c505a/c505ca data sheet 51 12.00 pin configuration in programming mode figure 27 p-mqfp-44 pin configuration of the c505a-4e/c505ca-4e in programming mode (top view) d4 d5 d6 d7 ea / v pp n.c. a5 / a13 prog a6 / a14 a7 psen a4 / a12 a3 / a11 a2 / a10 a1 / a9 a0 / a8 v dd xtal1 xtal2 n.c. n.c. v ss 33 34 35 36 37 38 39 40 41 42 43 44 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1234567 89 10 11 d3 d2 d1 n.c. n.c. n.c. n.c. n.c. n.c. d0 n.c. n.c. n.c. n.c. reset pmsel0 pmsel1 psel prd pale n.c. n.c. c505a-4e c505ca-4e
c505/c505c/c505a/c505ca data sheet 52 12.00 the following table 11 contains the functional description of all c505a-4e/c505ca-4e pins which are required for otp memory programming. table 11 pin definitions and functions in programming mode symbol pin number i/o *) function reset 4 i reset this input must be at static ? 1 ? (active) level during the whole programming mode. pmsel0 pmsel1 5 7 i i programming mode selection pins these pins are used to select the different access modes in programming mode. pmsel1,0 must satisfy a setup time to the rising edge of pale. when the logic level of pmsel1,0 is changed, pale must be at low level. psel 8i basic programming mode select this input is used for the basic programming mode selection and must be switched according figure 28 . prd 9i programming mode read strobe this input is used for read access control for otp memory read, version register read, and lock bit read operations. pale 10 i programming address latch enable pale is used to latch the high address lines. the high address lines must satisfy a setup and hold time to/from the falling edge of pale. pale must be at low level when the logic level of pmsel1,0 is changed. xtal2 14 o xtal2 output of the inverting oscillator amplifier. xtal1 15 i xtal1 input to the oscillator amplifier. v ss 16 ? circuit ground potential must be applied in programming mode. v dd 17 ? power supply terminal must be applied in programming mode. *) i = input o= output pmsel1 pmsel0 access mode 00reserved 0 1 read version bytes 1 0 program/read lock bits 1 1 program/read otp memory byte
c505/c505c/c505a/c505ca data sheet 53 12.00 p2.0-7 18-25 i address lines p2.0-7 are used as multiplexed address input lines a0-a7 and a8-a14. a8-a14 must be latched with pale. psen 26 i program store enable this input must be at static ? 0 ? level during the whole programming mode. prog 27 i programming mode write strobe this input is used in programming mode as a write strobe for otp memory program, and lock bit write operations during basic programming mode selection a low level must be applied to prog . ea /v pp 29 ? external access / programming voltage this pin must be at 11.5v (v pp ) voltage level during programming of an otp memory byte or lock bit. during an otp memory read operation this pin must be at v ih high level. this pin is also used for basic programming mode selection. at basic programming mode selection a low level must be applied to ea /v pp . d7-0 30-37 i/o data lines 0-7 during programming mode, data bytes are transferred via the bidirectional port 0 data lines. n.c. 1-3, 6, 11-13, 28, 38-44 ? not connected these pins should not be connected in programming mode. *) i = input o= output table 11 pin definitions and functions in programming mode (cont ? d) symbol pin number i/o *) function
c505/c505c/c505a/c505ca data sheet 54 12.00 basic programming mode selection the basic programming mode selection scheme is shown in figure 28 . figure 28 basic programming mode selection reset psen prog ea /v pp ? 1 ? ? 0 ? psel ? 0 ? v dd clock (xtal1/xtal2) 5v stable prd pale ? 1 ? ? 0 ? ready for access mode selection during this period signals are not actively driven 0v v ih v pp pmsel1,0 0,1
c505/c505c/c505a/c505ca data sheet 55 12.00 lock bits programming / read the c505a-4e/c505ca-4e has two programmable lock bits which, when programmed according to table 13 , provide four levels of protection for the on-chip otp code memory. the state of the lock bits can also be read. table 12 access modes selection access mode ea / v pp prog prd pmsel address (port 2) data (port 0) 10 program otp memory byte v pp hh h a0-7 a8-14 d0-7 read otp memory byte v ih h program otp lock bits v pp hh l ? d1,d0 see table 13 read otp lock bits v ih h read otp version byte v ih h l h byte addr. of sign. byte d0-7 table 13 lock bit protection types lock bits at d1,d0 protection level protection type d1 d0 1 1 level 0 the otp lock feature is disabled. during normal operation of the c505a-4e/c505ca-4e, the state of the ea pin is not latched on reset. 1 0 level 1 during normal operation of the c505a-4e/c505ca-4e, movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset. an otp memory read operation is only possible using the rom/otp verification mode 2 for protection level 1. further programming of the otp memory is disabled (reprogramming security). 0 1 level 2 same as level 1, but also otp memory read operation using otp verification mode is disabled. 0 0 level 3 same as level 2; but additionally external code execution by setting ea =low during normal operation of the c505a-4e/ c505ca-4e is no more possible. external code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the rom boundary), is still possible.
c505/c505c/c505a/c505ca data sheet 56 12.00 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. storage temperature t st ? 65 150 c ? voltage on v dd pins with respect to ground ( v ss ) v dd ? 0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in ? 0.5 v dd + 0.5 v ? input current on any pin during overload condition ? 10 10 ma ? absolute sum of all input currents during overload condition | 100 ma | ma ? power dissipation p diss 1w ?
c505/c505c/c505a/c505ca data sheet 57 12.00 parameter interpretation the parameters listed in the following partly represent the characteristics of the c505 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ? symbol ? : cc ( c ontroller c haracteristics): the logic of the c505 will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective characteristics to the c505. operating conditions parameter symbol limit values unit notes min. max. supply voltage v dd 4.25 5.5 v active mode, f osc max = 20 mhz 2 5.5 v powerdown mode ground voltage v ss 0 v reference voltage ambient temperature c ? sab-c505 t a 070 saf-c505 t a -40 85 sah-c505 t a -40 110 sak-c505 t a -40 125 analog reference voltage v aref 4 v dd + 0.1 v ? analog ground voltage v agnd v ss ? 0.1 v ss + 0.2 v ? analog input voltage v ain v agnd -0.2 v aref +0.2 v ? xtal clock f osc 220 (with 50% duty cycle) mhz 1) 1) for the extended temperature range -40 c to 110 c (sah) and -40 c to 125 c (sak), the devices c505-2r, c505-l, c505c-2r and c505c-l have the max. operating frequency of 16mhz with 50% clock duty cycle.
c505/c505c/c505a/c505ca data sheet 58 12.00 dc characteristics (operating conditions apply) notes see page 60 parameter symbol limit values unit test condition min. max. input low voltages all except ea , reset ea pin reset pin v il v il1 v il2 ? 0.5 ? 0.5 ? 0.5 0.2 v dd - 0.1 0.2 v dd - 0.3 0.2 v dd + 0.1 v v v ? ? ? input high voltages all except xtal1, reset xtal1 pin reset pin v ih v ih1 v ih2 0.2 v dd +0.9 0.7 v dd 0.6 v dd v dd + 0.5 v dd + 0.5 v dd + 0.5 v v v ? ? ? output low voltages ports 1, 2, 3, 4 port 0, ale, psen v ol v ol1 ? ? 0.45 0.45 v v i ol = 1.6 ma 1) i ol = 3.2 ma 1) output high voltages ports 1, 2, 3, 4 port 0 in external bus mode, ale, psen v oh v oh2 2.4 0.9 v dd 2.4 0.9 v dd ? ? ? ? v v v v i oh = ? 80 a i oh = ? 10 a i oh = ? 800 a i oh = ? 80 a 2) logic 0 input current ports 1, 2, 3, 4 i il ? 10 ? 70 a v in =0.45v logical 1-to-0 transition current ports 1, 2, 3, 4 i tl ? 65 ? 650 a v in =2v input leakage current port 0, an0-7 (port 1), ea i li ? 1 a0.45< v in < v dd input high current to reset i ih 5100 a 14) 0.6 v dd < v in < v dd pin capacitance c io ? 10 pf f c =1mhz, t a =25 c overload current i ov ? 5ma 3) 4) programming voltage v pp 10.9 12.1 v 11.5 v 5% 5) supply current at ea /v pp 30 ma 6)
c505/c505c/c505a/c505ca data sheet 59 12.00 power supply currents notes see page 60 parameter symbol limit values unit test condition typ. 12) max. 13) c505 / c505c active mode 12 mhz 20 mhz i dd i dd 19.3 31.3 27.0 39 ma 7) idle mode 12 mhz 20 mhz i dd i dd 10.3 16.2 13.0 21.0 ma 8) active mode with slow-down enabled 12 mhz 20 mhz i dd i dd 3.9 4.8 5.5 7.5 ma 9) idle mode with slow-down enabled 12 mhz 20 mhz i dd i dd 3.2 4.0 5.0 7.0 ma 10) power down mode i pd 10 50 a v dd = 2..5.5 v 11) c505a-4e /c505ca-4e active mode 16 mhz 20 mhz i dd i dd 28.7 35.2 30.7 37.6 ma 7) idle mode 16 mhz 20 mhz i dd i dd 14.9 17.7 15.9 18.9 ma 8) active mode with slow-down enabled 16 mhz 20 mhz i dd i dd 9.9 12.3 12.8 15.6 ma 9) idle mode with slow-down enabled 16 mhz 20 mhz i dd i dd 5.1 6.3 5.6 6.8 ma 10) power down mode i pd 5.6 20 a v dd = 2..5.5 v 11) c505a-4r / c505ca-4r /c505a-2r / c505ca-2r /c505a-l / c505ca-l active mode 16 mhz 20 mhz i dd i dd 22.8 27.6 29.2 35.3 ma 7) idle mode 16 mhz 20 mhz i dd i dd 12.7 15.0 16.3 19.3 ma 8) active mode with slow-down enabled 16 mhz 20 mhz i dd i dd 6.6 7.3 8.2 9.3 ma 9) idle mode with slow-down enabled 16 mhz 20 mhz i dd i dd 5.0 5.3 5.9 6.5 ma 10) power down mode i pd 5.3 30 a v dd = 2..5.5 v 11)
c505/c505c/c505a/c505ca data sheet 60 12.00 note: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address lines are stabilizing. 3) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > v dd +0.5v or v ov < v ss - 0.5 v). the absolute sum of input currents on all port pins may not exceed 50 ma. the supply voltage v dd and v ss must remain within the specified limits. 4) not 100% tested, guaranteed by design characterization. 5) only valid for c505a-4e and c505ca-4e. 6) only valid for c505a-4e and c505ca-4e in programming mode. 7) i dd (active mode) is measured with: xtal1 driven with t r , t f = 5 ns, 50% duty cycle , v il = v ss +0.5v, v ih = v dd ? 0.5 v; xtal2 = n.c.; ea =port 0=reset= v dd ; all other pins are disconnected. 8) i dd (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r , t f = 5 ns, 50% duty cycle, v il = v ss +0.5v, v ih = v dd ? 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v dd ; all other pins are disconnected; the microcontroller is put into idle mode by software; 9) i dd (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r , t f = 5 ns, 50% duty cycle, v il = v ss +0.5v, v ih = v dd ? 0.5 v; xtal2 = n.c.; reset = ea = v ss ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 10) i dd (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r , t f = 5 ns, 50% duty cycle, v il = v ss +0.5v, v ih = v dd ? 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v dd ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software; 11) i pd (power-down mode) is measured under following conditions: port 0 = e a = v dd ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; v agnd = v ss ; v aref = v dd ; all other pins are disconnected. 12) the typical i dd values are periodically measured at t a = +25 c but not 100% tested. 13) the maximum i dd values are measured under worst case conditions ( t a = 0 c or -40 c and v dd =5.5v) 14) the values are valid for c505ca-4r, c505ca-2r, c505ca-l, c505a-4r, c505a-2r and c505a-l only.
c505/c505c/c505a/c505ca data sheet 61 12.00 figure 29 i dd diagram of c505 and c505c c505/c505c : power supply current calculation formulas note: f osc is the oscillator frequency in mhz. i dd values are given in ma. parameter symbol formula active mode i dd typ i dd max 1.5 * f osc + 1.3 1.5 * f osc + 9.0 idle mode i dd typ i dd max 0.74 * f osc + 1.4 1.0 * f osc + 1.0 active mode with slow-down enabled i dd typ i dd max 0.11 * f osc + 2.6 0.25 * f osc + 2.5 idle mode with slow-down enabled i dd typ i dd max 0.1 * f osc + 2.0 0.25 * f osc + 2.0 i dd [ma] i dd max i dd typ 5 10 15 20 25 30 f osc [mhz] 12 8 420 16 c505 c505c 35 40 i d l e m o d e id l e m ode a c t i v e m o d e a c t i v e m o d e i d l e m o d e + s l o w - d o w n a c t ive m o d e +s lo w - d o wn
c505/c505c/c505a/c505ca data sheet 62 12.00 figure 30 i dd diagram of c505a-4e and c505ca-4e c505a-4e/c505ca-4e : power supply current calculation formulas note: f osc is the oscillator frequency in mhz. i dd values are given in ma. parameter symbol formula active mode i dd typ i dd max 1.63 * f osc + 2.6 1.74 * f osc + 2.8 idle mode i dd typ i dd max 0.69 * f osc + 3.9 0.74 * f osc + 4.1 active mode with slow-down enabled i dd typ i dd max 0.6 * f osc + 0.3 0.7 * f osc + 1.6 idle mode with slow-down enabled i dd typ i dd max 0.3 * f osc + 0.3 0.3 * f osc + 0.8 i dd [ma] i dd max i dd typ 5 10 15 20 25 30 f osc [mhz] 12 8 420 16 c505a-4e c505ca-4e 35 40 i d l e m o d e a c t i v e m o d e i d l e m od e+ s l ow - do w n a c t i v e m o d e + s l o w - d o w n
c505/c505c/c505a/c505ca data sheet 63 12.00 figure 31 i dd diagram of c505a-4r/c505a-2r/c505a-l/c505ca-4r/c505ca-2r/c505ca-l c505a-4r/c505a-2r/c505a-l/c505ca-4r/c505ca-2r/c505ca-l : power supply current calculation formulas note: f osc is the oscillator frequency in mhz. i dd values are given in ma. parameter symbol formula active mode i dd typ i dd max 1.19 * f osc + 3.77 1.54 * f osc + 4.47 idle mode i dd typ i dd max 0.57 * f osc + 3.55 0.75 * f osc + 4.26 active mode with slow-down enabled i dd typ i dd max 0.18 * f osc + 3.74 0.28 * f osc + 3.67 idle mode with slow-down enabled i dd typ i dd max 0.07 * f osc + 3.91 0.14 * f osc + 3.64 i dd [ma] i dd max i dd typ 5 10 15 20 25 30 f osc [mhz] 12 8 420 16 c505a-4r c505a-2r c505a-l c505ca-4r c505ca-2r c505ca-l 35 40 a c t i v e m o d e i d l e m o d e a c t i v e m o d e + s l o w - d o w n i d l e m o d e + s l o w - d o w n
c505/c505c/c505a/c505ca data sheet 64 12.00 a/d converter characteristics of c505 and c505c (operating conditions apply) notes see next page. clock calculation table : further timing conditions : t adc min = 800 ns t in = 1 / f osc = t clp parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd - 0.2 v aref + 0.2 v 1) sample time t s ? 64 x t in 32 x t in 16 x t in 8 x t in ns prescaler 32 prescaler 16 prescaler 8 prescaler 4 2) conversion cycle time t adcc ? 320 x t in 160 x t in 80 x t in 40 x t in ns prescaler 32 prescaler 16 prescaler 8 prescaler 4 3) total unadjusted error t ue ? 2lsbv ss +0.5v v ain v dd -0.5v 4) internal resistance of reference voltage source r aref ? t adc / 500 - 1 k ? t adc in [ns] 5) 6) internal resistance of analog source r asrc ? t s / 500 - 1 k ? t s in [ns] 2) 6) adc input capacitance c ain ? 50 pf 6) clock prescaler ratio adcl1, 0 t adc t s t adcc 32 1 1 32 x t in 64 x t in 320 x t in 16 1 0 16 x t in 32 x t in 160 x t in 8 0 1 8 x t in 16 x t in 80 x t in 4 0 0 4 x t in 8 x t in 40 x t in
c505/c505c/c505a/c505ca data sheet 65 12.00 note: 1) v ain may exeed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be 00 h or ff h , respectively. 2) during the sample time the input capacitance c ain must be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue (max.) is tested at ? 40 t a = 125 c ; v dd 5.5 v; v aref v dd + 0.1 v and v ss = v agnd . it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adc ? s capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
c505/c505c/c505a/c505ca data sheet 66 12.00 a/d converter characteristics of c505a and c505ca (operating conditions apply) notes see next page. clock calculation table : further timing conditions : t adc min = 500 ns t in = 1 / f osc = t clp parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) sample time t s ? 64 x t in 32 x t in 16 x t in 8 x t in ns prescaler 32 prescaler 16 prescaler 8 prescaler 4 2) conversion cycle time t adcc ? 384 x t in 192 x t in 96 x t in 48 x t in ns prescaler 32 prescaler 16 prescaler 8 prescaler 4 3) total unadjusted error t ue ? 2lsbv ss +0.5v v ain v dd -0.5v 4) ? 4lsbv ss < v ain < v dd +0.5v v dd - 0.5 v < v ain < v dd 4) internal resistance of reference voltage source r aref ? t adc / 250 - 0.25 k ? t adc in [ns] 5) 6) internal resistance of analog source r asrc ? t s / 500 - 0.25 k ? t s in [ns] 2) 6) adc input capacitance c ain ? 50 pf 6) clock prescaler ratio adcl1, 0 t adc t s t adcc 32 1 1 32 x t in 64 x t in 384 x t in 16 1 0 16 x t in 32 x t in 192 x t in 8 0 1 8 x t in 16 x t in 96 x t in 4 0 0 4 x t in 8 x t in 48 x t in
c505/c505c/c505a/c505ca data sheet 67 12.00 note: 1) v ain may exeed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c ain must be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v dd = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adc ? s capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
c505/c505c/c505a/c505ca data sheet 68 12.00 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c505 to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. ale pulse width t lhll 48 ? clp - 15 ? ns address setup to ale t avll 10 ? tcl hmin -15 ? ns address hold after ale t llax 10 ? tcl hmin -15 ? ns ale to valid instruction in t lliv ? 75 ? 2 clp - 50 ns ale to psen t llpl 10 ? tcl lmin -15 ? ns psen pulse width t plph 73 ? clp+ tcl hmin -15 ? ns psen to valid instruction in t pliv ? 38 ? clp+ tcl hmin - 50 ns input instruction hold after psen t pxix 0 ? 0 ? ns input instruction float after psen t pxiz *) ? 15 ? tcl lmin -10 ns address valid after psen t pxav *) 20 ? tcl lmin - 5 ? ns address to valid instruction in t aviv ? 95 ? 2 clp + tcl hmin -55 ns address float to psen t azpl -5 ? -5 ? ns
c505/c505c/c505a/c505ca data sheet 69 12.00 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle, cont ? d) external data memory characteristics parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. rd pulse width t rlrh 158 ? 3 clp - 30 ? ns wr pulse width t wlwh 158 ? 3 clp - 30 ? ns address hold after ale t llax2 48 ? clp - 15 ? ns rd to valid data in t rldv ? 100 ? 2 clp+ tcl hmin - 50 ns data hold after rd t rhdx 0 ? 0 ? ns data float after rd t rhdz ? 51 ? clp - 12 ns ale to valid data in t lldv ? 200 ? 4 clp - 50 ns address to valid data in t avdv ? 200 ? 4 clp + tcl hmin -75 ns ale to wr or rd t llwl 73 103 clp + tcl lmin - 15 clp+ tcl lmin + 15 ns address valid to wr t avwl 95 ? 2 clp - 30 ? ns wr or rd high to ale high t whlh 10 40 tcl hmin - 15 tcl hmin + 15 ns data valid to wr transition t qvwx 5 ? tcl lmin - 20 ? ns data setup before wr t qvwh 163 ? 3 clp + tcl lmin - 50 ? ns data hold after wr t whqx 5 ? tcl hmin - 20 ? ns address float after rd t rlaz ? 0 ? 0ns
c505/c505c/c505a/c505ca data sheet 70 12.00 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle, cont ? d) note: the 16 mhz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. external clock drive characteristics parameter symbol cpu clock = 16 mhz duty cycle 0.4 to 0.6 variable cpu clock 1/clp = 2 to 16 mhz unit min. max. min. max. oscillator period clp 62.5 62.5 62.5 500 ns high time tcl h 25 ? 25 clp - tcl l ns low time tcl l 25 ? 25 clp - tcl h ns rise time t r ? 10 ? 10 ns fall time t f ? 10 ? 10 ns oscillator duty cycle dc 0.4 0.6 25 / clp 1 - 25 / clp ? clock cycle tcl 25 37.5 clp * dc min clp * dc max ns
c505/c505c/c505a/c505ca data sheet 71 12.00 ac characteristics (20 mhz, 0.5 duty cycle) (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c505 to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. ale pulse width t lhll 35 ? clp - 15 ? ns address setup to ale t avll 10 ? clp/2 - 15 ? ns address hold after ale t llax 10 ? clp/2 - 15 ? ns ale to valid instruction in t lliv ? 55 ? 2 clp - 45 ns ale to psen t llpl 10 ? clp/2 - 15 ? ns psen pulse width t plph 60 ? 3/2 clp - 15 ? ns psen to valid instruction in t pliv ? 25 ? 3/2 clp - 50 ns input instruction hold after psen t pxix 0 ? 0 ? ns input instruction float after psen t pxiz *) ? 20 ? clp/2 - 5 ns address valid after psen t pxav *) 20 ? clp/2 - 5 ? ns address to valid instruction in t aviv ? 65 ? 5/2 clp - 60 ns address float to psen t azpl - 5 ? - 5 ? ns
c505/c505c/c505a/c505ca data sheet 72 12.00 ac characteristics (20 mhz, 0.5 duty cycle, cont ? d) external data memory characteristics parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. rd pulse width t rlrh 120 ? 3 clp - 30 ? ns wr pulse width t wlwh 120 ? 3 clp - 30 ? ns address hold after ale t llax2 35 ? clp - 15 ? ns rd to valid data in t rldv ? 75 ? 5/2 clp- 50 ns data hold after rd t rhdx 0 ? 0 ? ns data float after rd t rhdz ? 38 ? clp - 12 ns ale to valid data in t lldv ? 150 ? 4 clp - 50 ns address to valid data in t avdv ? 150 ? 9/2 clp - 75 ns ale to wr or rd t llwl 60 90 3/2 clp - 15 3/2 clp + 15 ns address valid to wr t avwl 70 ? 2 clp - 30 ? ns wr or rd high to ale high t whlh 10 40 clp/2 - 15 clp/2 + 15 ns data valid to wr transition t qvwx 5 ? clp/2 - 20 ? ns data setup before wr t qvwh 125 ? 7/2 clp - 50 ? ns data hold after wr t whqx 5 ? clp/2 - 20 ? ns address float after rd t rlaz ? 0 ? 0ns external clock drive characteristics parameter symbol limit values unit variable clock freq. = 2 mhz to 20 mhz min. max. oscillator period clp 50 500 ns high time tcl h 15 clp-tcl l ns low time tcl l 15 clp-tcl h ns rise time t r ? 10 ns fall time t f ? 10 ns oscillator duty cycle dc 0.5 0.5 ?
c505/c505c/c505a/c505ca data sheet 73 12.00 figure 32 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
c505/c505c/c505a/c505ca data sheet 74 12.00 figure 33 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
c505/c505c/c505a/c505ca data sheet 75 12.00 figure 34 data memory write cycle figure 35 external clock drive on xtal1 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph tcl h tcl l clp t r t f 0.2 v dd 0.7 dd v - 0.1 mct03310 xtal1 0.7 v dd 0.2 v dd - 0.1
c505/c505c/c505a/c505ca data sheet 76 12.00 ac characteristics of programming mode (c505a-4e and c505ca-4e only) v dd = 5 v 10 %; v pp = 11.5 v 5%; t a = 25 c 10 c parameter symbol limit values unit min. max. pale pulse width t paw 35 ? ns pmsel setup to pale rising edge t pms 10 ? address setup to pale, prog , or prd falling edge t pas 10 ? ns address hold after pale, prog , or prd falling edge t pah 10 ? ns address, data setup to prog or prd t pcs 100 ? ns address, data hold after prog or prd t pch 0 ? ns pmsel setup to prog or prd t pms 10 ? ns pmsel hold after prog or prd t pmh 10 ? ns prog pulse width t pww 100 ? s prd pulse width t prw 100 ? ns address to valid data out t pad ? 75 ns prd to valid data out t prd ? 20 ns data hold after prd t pdh 0 ? ns data float after prd t pdf ? 20 ns prog high between two consecutive prog low pulses t pwh1 1 ? s prd high between two consecutive prd low pulses t pwh2 100 ns xtal clock period t clkp 83.3 500 ns
c505/c505c/c505a/c505ca data sheet 77 12.00 figure 36 programming code byte - write cycle timing t paw t pms pah t pas t a8-a14 a0-a7 d0-d7 pcs t pww t pch t t pwh mct03642 h, h pale pmsel1,0 port 2 port 0 prog notes: prd must be high during a programming write cycle.
c505/c505c/c505a/c505ca data sheet 78 12.00 figure 37 verify code byte - read cycle timing t paw t pms pah t pas t a8-a14 a0-a7 pad t d0-d7 t pdh t pdf prd t pcs t prw t pch t t pwh mct03643 h, h pale pmsel1,0 port 2 port 0 prd prog must be high during a programming read cycle. notes:
c505/c505c/c505a/c505ca data sheet 79 12.00 figure 38 lock bit access timing figure 39 version byte read timing h, l h, l d0, d1 d0, d1 t pcs pms t pmh t t pch pww t pms t prd t t pdh pdf t pmh t prw t mct03644 pmsel1,0 port 0 prog prd pale should be low during a lock bit read / write cycle. note: e. g. fd d0-7 t pcs pms t t pdh pdf t pmh t mct03645 port 2 port 0 prd pmsel1,0 l, h h prw t prd t pch t prog must be high during a programming read cycle. note:
c505/c505c/c505a/c505ca data sheet 80 12.00 rom/otp verification characteristics for c505 rom verification mode 1 (c505(c)(a)-2r and c505(c)a-4r only) figure 40 rom verification mode 1 parameter symbol limit values unit min. max. address to valid data t avqv ? 5 clp ns p1.0 - p1.7 p2.0 - p2.6 port 0 address data out address: p1.0 - p1.7 = a0 - a7 p2.0 - p2.5 = a8 - a14 data: p0.0 - p0.7 = d0 - d7 inputs: p2.6, p2.7, psen = ale, ea = reset = v ss v ih v ih2 avqv t mct03693 p2.6 p2.7, psen = v ss ale, ea = v ih reset = v ih2 inputs: note: p2.6 should be connected to v ss for c505(c)(a)-2r
c505/c505c/c505a/c505ca data sheet 81 12.00 rom/otp verification characteristics for c505 (cont ? d) rom/otp verification mode 2 figure 41 rom/otp verification mode 2 parameter symbol limit values unit min. typ max. ale pulse width t awd ? clp ? ns ale period t acy ? 6 clp ? ns data valid after ale t dva ?? 2 clp ns data stable after ale t dsa 4 clp ?? ns p3.5 setup to ale low t as ? t cl ? ns oscillator frequency 1/ clp 4 ? 6mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
c505/c505c/c505a/c505ca data sheet 82 12.00 figure 42 ac testing: input, output waveforms figure 43 ac testing : float waveforms figure 44 recommended oscillator circuits for crystal oscillator 0.45 v v dd 0.2 -0.1 +0.9 0.2 dd v test points mct00039 v dd -0.5 v ac inputs during testing are driven at v dd - 0.5 v for a logic ? 1 ? and 0.45 v for a logic ? 0 ? . timing measurements are made at v ihmin for a logic ? 1 ? and v ilmax for a logic ? 0 ? . mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh ? 20 ma mcs03311 c 2 - 20 mhz xtal2 xtal1 xtal1 xtal2 n.c. external oscillator signal crystal oscillator mode driving from external source crystal mode: c = 20 pf 10 pf (incl. stray capacitance) c
c505/c505c/c505a/c505ca data sheet 83 12.00 figure 45 p-mqfp-44 package outline p-mqfp-44-2 (smd) (plastic metric quad flat package) gpm05622 sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? dimensions in mm smd = surface mounted device
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